1. Field of the Invention
The present invention relates to a method and system for glitch correction in an all digital phase lock loop.
2. Description of Related Art
Conventional all digital phase lock loops utilizing a multi-phase oscillator generate a fractional phase signal and an integer phase signal which are summed to form a phase signal. The phase signal is compared with a reference phase signal and the difference is taken to determine a phase error signal. However, in generating the fractional phase signal and the integer phase signal, conventional phase lock loops can have two different paths.
The two different paths can have different delay times in generating the fractional phase signal or the integer phase signal when clocked by a reference clock signal. This can result in the fractional phase signal and the integer phase signal being misaligned. The misalignment in the fractional phase signal and the integer phase signal can be problematic since the sum is used to generate the phase signal. The phase signal can have glitches where the integer phase signal has already been incremented, but the fractional phase signal has not yet been reset to 0. This leads to the phase signal being off by the increment of the integer phase signal since the integer phase signal was prematurely incremented for a short period of time.
Such glitches in the phase signal are propagated through to the phase error signal and can reduce the efficiency and/or the performance of the phase lock loop. In addition, the phase lock loop may encounter problems when attempting to remain in compliance with a specification, such as those propagated by the 3rd Generation Partnership Project (“3GPP”).
Thus, there is a need for a method and system for glitch correction in an all digital phase lock loop.